1. Field of the Invention
The present invention generally relates to a DRAM (Dynamic Random Access Memory), and more particularly to a data path architecture for a DRAM.
2. Description of the Prior Art
Major design efforts have been directed at minimizing the chip area required for memory array cells. A number of solutions have been proposed, including methods to reduce overall chip area by reducing the number of circuits required in the layout. The following inventions illustrate integrated circuit memories that increase memory capacity while meeting minimum spacing requirements.
U.S. Pat. No. 5,774,408 to Shirley teaches a DRAM architecture where sense amplifiers are shared between memory cells. The invention reduces layout area by arranging sense amplifiers to minimize die area. The sense amplifiers are laid out in a region between memory array portions having memory cells that are each coupled to a digit line in a plurality of alternating sequenced digit line pairs.
U.S. Pat. No. 5,966,338 to Liu et al shows a DRAM with a staggered, bit line sense amplifier configuration with shared sense amplifiers. External sense amplifiers have output terminals, which are shorted together in pairs. The invention utilizes an input/output (I/O) data path scheme, which reduces the time delay through the array and simplifies the I/O data path as compared to the prior art.
Random access memories (RAM) such as a dynamic random access memory (DRAM), static random access memory (SRAM), and read only memory (ROM) are generally structured as shown in FIGS. 1a–1c. A memory integrated circuit is shown in FIG. 1a as having multiple independent memory array units MAU Each memory array unit is formed of groups of memory blocks MB<0>, . . . ,MB<n>. The memory block MB<R> acts as a redundant or spare block that can be configured to replace non-functioning areas of the remaining memory block MB<n>. FIG. 1a shows the input/output circuits (I/O CKT) represented by the small squares which are in the middle of the memory integrated circuit (MEMIC).
The bank of main data line sense amplifiers MDQSA sense the memory data signal from the selected memory blocks MB<O>, . . . , MB<n>, amplify, and convert the memory data signal to a signal level acceptable by the 110 circuitry of the memory integrated circuit. The input to each main data line sense amplifier of the bank of data line sense amplifiers MDQSA is a pair of main data lines MDQ that are connected to each of the memory blocks MB<O>, . . . , MB<n>.
Each memory block MB<O>, . . . , MB<n> is divided into a group of memory segments MSEG<O>, . . . , MSEG<n>. As shown in FIG. 1b, each memory segment is constructed of multiple sub-arrays. The structure of each memory sub-array, as shown in FIG. 1c has an array of memory cells arranged in rows and columns. At the periphery of the array of memory cells is a bank of bit line sense amplifiers SA. The output of each of the bit line sense amplifiers is coupled to a pair of local data lines LDQ1, . . . , LDQ4 through the bit switches BS1, . . . , BSn. In turn, the local data lines LDQ1 . . . , LDQ4 are selectively coupled to the main data lines MDQ1, . . . ,MDQ4 and thus to the main data line sense amplifiers. FIG. 1b also shows the adjacent data lines (ADiMDQ), which are the data lines which can affect the operation of the MDQ1–3 data lines and their support circuitry.
The main data switches MDSW1, . . . , MDSWn provide the selective connecting of the local data lines LDQ1, . . . ,LDQ4 to the main data line sense amplifiers. As shown, each main data line MDQ1, . . . , MDQ4 is connected through a main data switch MDSW1, . . . , MDSWN to the local data lines LDQ1, . . . ,LDQ4 for each memory block MB<n>. When memory cells within a memory block MB<0>, . . . , MB<n> are selected, the appropriate bit switches BS0, . . . , BSn and the appropriate main data switches MDSW1, . . . ,MDSWn are activated to insure that the selected memory cells are coupled to the main data line sense amplifiers MDQSA.
To avoid corruption of the memory data signals from the selected data cells, the bit switches BS0, . . . , BSn and the main data switches MDSW1, . . . , MDSWn must be activated such that only one memory cell is coupled to a main data line sense amplifier MDQSA. The rows of memory cells within each sub-array are activated by the word line control signals WL0, WL1, . . . , WLi.
The rows of memory cells within each sub-array are activated by the word line control signals WLO, WLI, . . . , WLi.
FIG. 1c shows the following components. SWENn are switch enable signals which enable pairs of bit lines to be read. Mn are memory cells. MDQSAn are sense amplifiers. BSn are bit sense lines. SEL ADDR is a select address control line. LDQn are load data lines to enable the reading of selected bit lines. SW CTRL is a switch control macro. BIT SW SEL is a bit switch select macro. BLmn are bit lines from an m by n matrix of bit lines. MCn are memory cells. SA are sense amplifiers.
The importance of reducing cost per bit of memory has led to a continuing search for simpler, smaller-area memory cells that could be more densely packaged on a chip. Memory cells with reduced complexity, area, and power consumption can be designed if dynamic MOS circuit concepts are used. Dynamic cells store binary data on a capacitance. Since normal leakage currents remove stored charge quickly, dynamic memories require periodic refreshing of stored charge. Additional circuit design techniques can be utilized to further reduce required chip area, as shown by the following invention.